1. Field of the Invention
The present invention relates to a manufacturing method for a strained silicon substrate wafer and more particularly to manufacturing method for a strained silicon substrate wafer having a lower threading dislocation and defect density than ever.
2. Description of the Related Art
In recent years, there has been a growing demand for high speed semiconductor devices requiring reduced consumption power. However, further enhancement of performance of devices by drastic scale reduction of devices, i.e., drastic reduction of dimension of element and fine division of element has been already physically limited.
Therefore, as a substrate for forming high speed semiconductor devices requiring reduced consumption power, there has been noted a semiconductor substrate having a strained silicon layer. In particular, a high speed device comprising as a channel region of a strained silicon layer (hereinafter referred to as “strain Si layer”) obtained by allowing silicon to undergo epitaxial growth on a silicon substrate with a silicon-germanium layer (hereinafter referred to as “SiGe layer”) interposed therebetween has been proposed and noted.
An MOS device comprising a Si/SiGe heterostructure has been noted as a favorable technique in the art of high driving power transistor requiring reduced consumption power because the channel mobility can be enhanced.
Further, the strain Si channel formed by allowing a Si layer to undergo epitaxial growth on a SiGe layer can provide a high current driving power regardless of which it is n-type or p-type. Therefore, a semiconductor substrate having a strain Si layer formed on a SiGe layer has been expected as a strain Si MOSFET technique.
This Si strained layer undergoes tensile strain caused by the SiGe layer having a greater lattice constant than silicon. This strain causes the change of the band structure of Si, releasing degeneration and hence enhancing carrier mobility.
Accordingly, the use of this strain Si layer as a channel region makes it possible to raise the carrier mobility by a factor of 1.5 or more rather than the use of bulk Si.
In order to obtain a good quality strain Si layer, it is necessary that a SiGe layer having a good quality, i.e., strain-relaxed SiGe layer having low threading dislocation and defect densities and a smooth surface be allowed to undergo epitaxial growth on the silicon substrate.
However, when a SiGe layer having a Ge composition ratio of 30% is formed directly on the silicon substrate, misfit dislocation is formed by strain energy because there is about 4% of crystalline lattice mismatching between Si and Ge. Many threading dislocations are then climbed up to Si channel layer, deteriorating the quality of crystal. It is thus made obvious that these threading dislocations cause the reduction of carrier mobility.
In the case where epitaxial growth is effected in a normal state, it goes without saying that even if the surface of Si is oxidized or annealed at high temperature before epitaxial growth, threading dislocation or misfit dislocation often occurs during epitaxial growth, making it impossible to obtain a good epitaxially grown layer.
Accordingly, it is desired to reduce the threading dislocation density to be climbed up to Si channel layer.
In the related art, in order to reduce the aforementioned threading dislocation, a process has been employed which comprises forming a graded SiGe layer which increases its Ge composition ratio with the thickness of growth on a silicon substrate, allowing the generation of dislocation in the composition graded layer to relax lattice, forming an SiGe buffer layer having a constant Ge composition ratio on the SiGe composition graded layer, and then forming a strain Si layer on the SiGe buffer layer (see, e.g., Japanese Patent Unexamined Publication JP-A-6-252046).
Further, a process has been proposed which comprises allowing epitaxial growth with a gradient of Ge concentration in the direction of thickness of SiGe layer to relax the magnitude of stain caused by the difference of lattice constant within a tolerance of generation of misfit dislocation.
As a proposal from the same idea as mentioned above, there is disclosed in Japanese Patent Unexamined Publication JP-A-2003-78116 and JP-A-2003-78118 (line 20, 5th column—line 28, 6th column page 4), an invention which comprises forming an SiGe layer in stages where the concentration of Ge has a gradation to inhibit frequent generation of dislocation by lattice mismatching.
However, even when this process is used to raise the concentration of Ge to 0.3 or more, the gradient of concentration becomes steep, making it impossible to inhibit the generation of dislocation to a satisfactory extent.
The thickness of the strain relaxation layer formed to avoid these unmetastable problems reaches about 3 μm (critical layer thickness), causing a new disadvantage that a crosshatched unevenness is formed on the surface of the SiGe layer in addition to poor production efficiency.
However, the sum of the thickness of SiGe composition graded layer and SiGe buffer layer having a constant composition is needed to be several micrometers. The formation of such a thick SiGe layer requires much time. Thus, the aforementioned process can difficultly be considered to be a proper process which can be industrially made the use of from the standpoint of production efficiency and cost as well.
Thus, a technique for effectively generating dislocation while the thickness of SiGe layer is low to relax strain has been desired.
As mentioned above, the related art technique is not capable of inhibiting the generation of misfit dislocation during epitaxial growth even if the surface of the silicon substrate is oxidized or annealed at high temperature before the epitaxial growth of SiGe layer.
Further, even when epitaxial growth is affected with a gradient of Ge concentration, threading dislocation occurs and defects such as generation of crosshatched unevenness on the surface of SiGe layer cannot be avoided.
Under these circumstances, it has been keenly desired to develop an effective means of preventing the generation of misfit dislocation and threading dislocation during epitaxial growth in the aforementioned process for the production of a strained silicon substrate wafer.